/*
 * Copyright (c) 2024 Syntiant Corp.  All rights reserved.
 * Contact at http://www.syntiant.com
 *
 * This software is available to you under a choice of one of two licenses.
 * You may choose to be licensed under the terms of the GNU General Public
 * License (GPL) Version 2, available from the file LICENSE in the main
 * directory of this source tree, or the OpenIB.org BSD license below.  Any
 * code involving Linux software will require selection of the GNU General
 * Public License (GPL) Version 2.
 *
 * OPENIB.ORG BSD LICENSE
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 	** SDK: v112.3.5-Samsung **
*/
#ifndef NDP120_SPI_REGS_H
#define NDP120_SPI_REGS_H

/*
 * block ndp120_spi, base 0x00000000
 */
#define NDP120_SPI 0x00U
#define NDP120_SPI_SIZE 0x80U
/* register ndp120_spi.id0 */
#define NDP120_SPI_ID0 0x00U
#define NDP120_SPI_ID0_SERIAL_BOOT_SHIFT 0
#define NDP120_SPI_ID0_SERIAL_BOOT_MASK 0x01U
#define NDP120_SPI_ID0_SERIAL_BOOT(v) \
        ((v) << NDP120_SPI_ID0_SERIAL_BOOT_SHIFT)
#define NDP120_SPI_ID0_SERIAL_BOOT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_ID0_SERIAL_BOOT_SHIFT))
#define NDP120_SPI_ID0_SERIAL_BOOT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_ID0_SERIAL_BOOT_MASK) | ((v) << NDP120_SPI_ID0_SERIAL_BOOT_SHIFT))
#define NDP120_SPI_ID0_SERIAL_BOOT_EXTRACT(x) \
        (((x) & NDP120_SPI_ID0_SERIAL_BOOT_MASK) >> NDP120_SPI_ID0_SERIAL_BOOT_SHIFT)
#define NDP120_SPI_ID0_AUTH_FIRMWARE_SHIFT 1
#define NDP120_SPI_ID0_AUTH_FIRMWARE_MASK 0x02U
#define NDP120_SPI_ID0_AUTH_FIRMWARE(v) \
        ((v) << NDP120_SPI_ID0_AUTH_FIRMWARE_SHIFT)
#define NDP120_SPI_ID0_AUTH_FIRMWARE_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_ID0_AUTH_FIRMWARE_SHIFT))
#define NDP120_SPI_ID0_AUTH_FIRMWARE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_ID0_AUTH_FIRMWARE_MASK) | ((v) << NDP120_SPI_ID0_AUTH_FIRMWARE_SHIFT))
#define NDP120_SPI_ID0_AUTH_FIRMWARE_EXTRACT(x) \
        (((x) & NDP120_SPI_ID0_AUTH_FIRMWARE_MASK) >> NDP120_SPI_ID0_AUTH_FIRMWARE_SHIFT)
#define NDP120_SPI_ID0_DEVICE_ID_SHIFT 2
#define NDP120_SPI_ID0_DEVICE_ID_MASK 0xfcU
#define NDP120_SPI_ID0_DEVICE_ID(v) \
        ((v) << NDP120_SPI_ID0_DEVICE_ID_SHIFT)
#define NDP120_SPI_ID0_DEVICE_ID_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_ID0_DEVICE_ID_SHIFT))
#define NDP120_SPI_ID0_DEVICE_ID_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_ID0_DEVICE_ID_MASK) | ((v) << NDP120_SPI_ID0_DEVICE_ID_SHIFT))
#define NDP120_SPI_ID0_DEVICE_ID_EXTRACT(x) \
        (((x) & NDP120_SPI_ID0_DEVICE_ID_MASK) >> NDP120_SPI_ID0_DEVICE_ID_SHIFT)
/* register ndp120_spi.id1 */
#define NDP120_SPI_ID1 0x01U
/* register ndp120_spi.intsts */
#define NDP120_SPI_INTSTS 0x02U
#define NDP120_SPI_INTSTS_MATCH_INT_SHIFT 0
#define NDP120_SPI_INTSTS_MATCH_INT_MASK 0x01U
#define NDP120_SPI_INTSTS_MATCH_INT(v) \
        ((v) << NDP120_SPI_INTSTS_MATCH_INT_SHIFT)
#define NDP120_SPI_INTSTS_MATCH_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_MATCH_INT_SHIFT))
#define NDP120_SPI_INTSTS_MATCH_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_MATCH_INT_MASK) | ((v) << NDP120_SPI_INTSTS_MATCH_INT_SHIFT))
#define NDP120_SPI_INTSTS_MATCH_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_MATCH_INT_MASK) >> NDP120_SPI_INTSTS_MATCH_INT_SHIFT)
#define NDP120_SPI_INTSTS_MATCH_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_MBIN_INT_SHIFT 1
#define NDP120_SPI_INTSTS_MBIN_INT_MASK 0x02U
#define NDP120_SPI_INTSTS_MBIN_INT(v) \
        ((v) << NDP120_SPI_INTSTS_MBIN_INT_SHIFT)
#define NDP120_SPI_INTSTS_MBIN_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_MBIN_INT_SHIFT))
#define NDP120_SPI_INTSTS_MBIN_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_MBIN_INT_MASK) | ((v) << NDP120_SPI_INTSTS_MBIN_INT_SHIFT))
#define NDP120_SPI_INTSTS_MBIN_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_MBIN_INT_MASK) >> NDP120_SPI_INTSTS_MBIN_INT_SHIFT)
#define NDP120_SPI_INTSTS_MBIN_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_MBOUT_INT_SHIFT 2
#define NDP120_SPI_INTSTS_MBOUT_INT_MASK 0x04U
#define NDP120_SPI_INTSTS_MBOUT_INT(v) \
        ((v) << NDP120_SPI_INTSTS_MBOUT_INT_SHIFT)
#define NDP120_SPI_INTSTS_MBOUT_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_MBOUT_INT_SHIFT))
#define NDP120_SPI_INTSTS_MBOUT_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_MBOUT_INT_MASK) | ((v) << NDP120_SPI_INTSTS_MBOUT_INT_SHIFT))
#define NDP120_SPI_INTSTS_MBOUT_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_MBOUT_INT_MASK) >> NDP120_SPI_INTSTS_MBOUT_INT_SHIFT)
#define NDP120_SPI_INTSTS_MBOUT_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_DNN_INT_SHIFT 3
#define NDP120_SPI_INTSTS_DNN_INT_MASK 0x08U
#define NDP120_SPI_INTSTS_DNN_INT(v) \
        ((v) << NDP120_SPI_INTSTS_DNN_INT_SHIFT)
#define NDP120_SPI_INTSTS_DNN_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_DNN_INT_SHIFT))
#define NDP120_SPI_INTSTS_DNN_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_DNN_INT_MASK) | ((v) << NDP120_SPI_INTSTS_DNN_INT_SHIFT))
#define NDP120_SPI_INTSTS_DNN_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_DNN_INT_MASK) >> NDP120_SPI_INTSTS_DNN_INT_SHIFT)
#define NDP120_SPI_INTSTS_DNN_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_FEATURE_INT_SHIFT 4
#define NDP120_SPI_INTSTS_FEATURE_INT_MASK 0x10U
#define NDP120_SPI_INTSTS_FEATURE_INT(v) \
        ((v) << NDP120_SPI_INTSTS_FEATURE_INT_SHIFT)
#define NDP120_SPI_INTSTS_FEATURE_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_FEATURE_INT_SHIFT))
#define NDP120_SPI_INTSTS_FEATURE_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_FEATURE_INT_MASK) | ((v) << NDP120_SPI_INTSTS_FEATURE_INT_SHIFT))
#define NDP120_SPI_INTSTS_FEATURE_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_FEATURE_INT_MASK) >> NDP120_SPI_INTSTS_FEATURE_INT_SHIFT)
#define NDP120_SPI_INTSTS_FEATURE_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_AE_INT_SHIFT 5
#define NDP120_SPI_INTSTS_AE_INT_MASK 0x20U
#define NDP120_SPI_INTSTS_AE_INT(v) \
        ((v) << NDP120_SPI_INTSTS_AE_INT_SHIFT)
#define NDP120_SPI_INTSTS_AE_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_AE_INT_SHIFT))
#define NDP120_SPI_INTSTS_AE_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_AE_INT_MASK) | ((v) << NDP120_SPI_INTSTS_AE_INT_SHIFT))
#define NDP120_SPI_INTSTS_AE_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_AE_INT_MASK) >> NDP120_SPI_INTSTS_AE_INT_SHIFT)
#define NDP120_SPI_INTSTS_AE_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_WM_INT_SHIFT 6
#define NDP120_SPI_INTSTS_WM_INT_MASK 0x40U
#define NDP120_SPI_INTSTS_WM_INT(v) \
        ((v) << NDP120_SPI_INTSTS_WM_INT_SHIFT)
#define NDP120_SPI_INTSTS_WM_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_WM_INT_SHIFT))
#define NDP120_SPI_INTSTS_WM_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_WM_INT_MASK) | ((v) << NDP120_SPI_INTSTS_WM_INT_SHIFT))
#define NDP120_SPI_INTSTS_WM_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_WM_INT_MASK) >> NDP120_SPI_INTSTS_WM_INT_SHIFT)
#define NDP120_SPI_INTSTS_WM_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_RF_INT_SHIFT 7
#define NDP120_SPI_INTSTS_RF_INT_MASK 0x80U
#define NDP120_SPI_INTSTS_RF_INT(v) \
        ((v) << NDP120_SPI_INTSTS_RF_INT_SHIFT)
#define NDP120_SPI_INTSTS_RF_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTSTS_RF_INT_SHIFT))
#define NDP120_SPI_INTSTS_RF_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTSTS_RF_INT_MASK) | ((v) << NDP120_SPI_INTSTS_RF_INT_SHIFT))
#define NDP120_SPI_INTSTS_RF_INT_EXTRACT(x) \
        (((x) & NDP120_SPI_INTSTS_RF_INT_MASK) >> NDP120_SPI_INTSTS_RF_INT_SHIFT)
#define NDP120_SPI_INTSTS_RF_INT_DEFAULT 0x00000000U
#define NDP120_SPI_INTSTS_DEFAULT 0x00000000U 
/* register ndp120_spi.matchsts */
#define NDP120_SPI_MATCHSTS 0x03U
#define NDP120_SPI_MATCHSTS_STATUS_SHIFT 0
#define NDP120_SPI_MATCHSTS_STATUS_MASK 0xffU
#define NDP120_SPI_MATCHSTS_STATUS(v) \
        ((v) << NDP120_SPI_MATCHSTS_STATUS_SHIFT)
#define NDP120_SPI_MATCHSTS_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_MATCHSTS_STATUS_SHIFT))
#define NDP120_SPI_MATCHSTS_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_MATCHSTS_STATUS_MASK) | ((v) << NDP120_SPI_MATCHSTS_STATUS_SHIFT))
#define NDP120_SPI_MATCHSTS_STATUS_EXTRACT(x) \
        (((x) & NDP120_SPI_MATCHSTS_STATUS_MASK) >> NDP120_SPI_MATCHSTS_STATUS_SHIFT)
/* register ndp120_spi.dnnsts */
#define NDP120_SPI_DNNSTS 0x04U
#define NDP120_SPI_DNNSTS_STATUS_SHIFT 0
#define NDP120_SPI_DNNSTS_STATUS_MASK 0xffU
#define NDP120_SPI_DNNSTS_STATUS(v) \
        ((v) << NDP120_SPI_DNNSTS_STATUS_SHIFT)
#define NDP120_SPI_DNNSTS_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_DNNSTS_STATUS_SHIFT))
#define NDP120_SPI_DNNSTS_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_DNNSTS_STATUS_MASK) | ((v) << NDP120_SPI_DNNSTS_STATUS_SHIFT))
#define NDP120_SPI_DNNSTS_STATUS_EXTRACT(x) \
        (((x) & NDP120_SPI_DNNSTS_STATUS_MASK) >> NDP120_SPI_DNNSTS_STATUS_SHIFT)
/* register ndp120_spi.featurests */
#define NDP120_SPI_FEATURESTS 0x05U
#define NDP120_SPI_FEATURESTS_STATUS_SHIFT 0
#define NDP120_SPI_FEATURESTS_STATUS_MASK 0xffU
#define NDP120_SPI_FEATURESTS_STATUS(v) \
        ((v) << NDP120_SPI_FEATURESTS_STATUS_SHIFT)
#define NDP120_SPI_FEATURESTS_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_FEATURESTS_STATUS_SHIFT))
#define NDP120_SPI_FEATURESTS_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_FEATURESTS_STATUS_MASK) | ((v) << NDP120_SPI_FEATURESTS_STATUS_SHIFT))
#define NDP120_SPI_FEATURESTS_STATUS_EXTRACT(x) \
        (((x) & NDP120_SPI_FEATURESTS_STATUS_MASK) >> NDP120_SPI_FEATURESTS_STATUS_SHIFT)
/* register ndp120_spi.intctl */
#define NDP120_SPI_INTCTL 0x10U
#define NDP120_SPI_INTCTL_MATCH_INTEN_SHIFT 0
#define NDP120_SPI_INTCTL_MATCH_INTEN_MASK 0x01U
#define NDP120_SPI_INTCTL_MATCH_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_MATCH_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_MATCH_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_MATCH_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_MATCH_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_MATCH_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_MATCH_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_MATCH_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_MATCH_INTEN_MASK) >> NDP120_SPI_INTCTL_MATCH_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_MATCH_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_MBIN_INTEN_SHIFT 1
#define NDP120_SPI_INTCTL_MBIN_INTEN_MASK 0x02U
#define NDP120_SPI_INTCTL_MBIN_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_MBIN_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_MBIN_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_MBIN_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_MBIN_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_MBIN_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_MBIN_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_MBIN_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_MBIN_INTEN_MASK) >> NDP120_SPI_INTCTL_MBIN_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_MBIN_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_MBOUT_INTEN_SHIFT 2
#define NDP120_SPI_INTCTL_MBOUT_INTEN_MASK 0x04U
#define NDP120_SPI_INTCTL_MBOUT_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_MBOUT_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_MBOUT_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_MBOUT_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_MBOUT_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_MBOUT_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_MBOUT_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_MBOUT_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_MBOUT_INTEN_MASK) >> NDP120_SPI_INTCTL_MBOUT_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_MBOUT_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_DNN_INTEN_SHIFT 3
#define NDP120_SPI_INTCTL_DNN_INTEN_MASK 0x08U
#define NDP120_SPI_INTCTL_DNN_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_DNN_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_DNN_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_DNN_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_DNN_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_DNN_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_DNN_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_DNN_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_DNN_INTEN_MASK) >> NDP120_SPI_INTCTL_DNN_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_DNN_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_FEATURE_INTEN_SHIFT 4
#define NDP120_SPI_INTCTL_FEATURE_INTEN_MASK 0x10U
#define NDP120_SPI_INTCTL_FEATURE_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_FEATURE_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_FEATURE_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_FEATURE_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_FEATURE_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_FEATURE_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_FEATURE_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_FEATURE_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_FEATURE_INTEN_MASK) >> NDP120_SPI_INTCTL_FEATURE_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_FEATURE_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_AE_INTEN_SHIFT 5
#define NDP120_SPI_INTCTL_AE_INTEN_MASK 0x20U
#define NDP120_SPI_INTCTL_AE_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_AE_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_AE_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_AE_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_AE_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_AE_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_AE_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_AE_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_AE_INTEN_MASK) >> NDP120_SPI_INTCTL_AE_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_AE_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_WM_INTEN_SHIFT 6
#define NDP120_SPI_INTCTL_WM_INTEN_MASK 0x40U
#define NDP120_SPI_INTCTL_WM_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_WM_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_WM_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_WM_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_WM_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_WM_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_WM_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_WM_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_WM_INTEN_MASK) >> NDP120_SPI_INTCTL_WM_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_WM_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_RF_INTEN_SHIFT 7
#define NDP120_SPI_INTCTL_RF_INTEN_MASK 0x80U
#define NDP120_SPI_INTCTL_RF_INTEN(v) \
        ((v) << NDP120_SPI_INTCTL_RF_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_RF_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_INTCTL_RF_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_RF_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_INTCTL_RF_INTEN_MASK) | ((v) << NDP120_SPI_INTCTL_RF_INTEN_SHIFT))
#define NDP120_SPI_INTCTL_RF_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_INTCTL_RF_INTEN_MASK) >> NDP120_SPI_INTCTL_RF_INTEN_SHIFT)
#define NDP120_SPI_INTCTL_RF_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_INTCTL_DEFAULT 0x00000000U 
/* register ndp120_spi.ctl */
#define NDP120_SPI_CTL 0x11U
#define NDP120_SPI_CTL_RESETN_SHIFT 0
#define NDP120_SPI_CTL_RESETN_MASK 0x01U
#define NDP120_SPI_CTL_RESETN(v) \
        ((v) << NDP120_SPI_CTL_RESETN_SHIFT)
#define NDP120_SPI_CTL_RESETN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_RESETN_SHIFT))
#define NDP120_SPI_CTL_RESETN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_RESETN_MASK) | ((v) << NDP120_SPI_CTL_RESETN_SHIFT))
#define NDP120_SPI_CTL_RESETN_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_RESETN_MASK) >> NDP120_SPI_CTL_RESETN_SHIFT)
#define NDP120_SPI_CTL_RESETN_DEFAULT 0x00000001U
#define NDP120_SPI_CTL_PORSTN_SHIFT 1
#define NDP120_SPI_CTL_PORSTN_MASK 0x02U
#define NDP120_SPI_CTL_PORSTN(v) \
        ((v) << NDP120_SPI_CTL_PORSTN_SHIFT)
#define NDP120_SPI_CTL_PORSTN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_PORSTN_SHIFT))
#define NDP120_SPI_CTL_PORSTN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_PORSTN_MASK) | ((v) << NDP120_SPI_CTL_PORSTN_SHIFT))
#define NDP120_SPI_CTL_PORSTN_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_PORSTN_MASK) >> NDP120_SPI_CTL_PORSTN_SHIFT)
#define NDP120_SPI_CTL_PORSTN_DEFAULT 0x00000001U
#define NDP120_SPI_CTL_CLKEN_SHIFT 2
#define NDP120_SPI_CTL_CLKEN_MASK 0x04U
#define NDP120_SPI_CTL_CLKEN(v) \
        ((v) << NDP120_SPI_CTL_CLKEN_SHIFT)
#define NDP120_SPI_CTL_CLKEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_CLKEN_SHIFT))
#define NDP120_SPI_CTL_CLKEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_CLKEN_MASK) | ((v) << NDP120_SPI_CTL_CLKEN_SHIFT))
#define NDP120_SPI_CTL_CLKEN_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_CLKEN_MASK) >> NDP120_SPI_CTL_CLKEN_SHIFT)
#define NDP120_SPI_CTL_CLKEN_DEFAULT 0x00000001U
#define NDP120_SPI_CTL_MCUHALT_SHIFT 3
#define NDP120_SPI_CTL_MCUHALT_MASK 0x08U
#define NDP120_SPI_CTL_MCUHALT(v) \
        ((v) << NDP120_SPI_CTL_MCUHALT_SHIFT)
#define NDP120_SPI_CTL_MCUHALT_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_MCUHALT_SHIFT))
#define NDP120_SPI_CTL_MCUHALT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_MCUHALT_MASK) | ((v) << NDP120_SPI_CTL_MCUHALT_SHIFT))
#define NDP120_SPI_CTL_MCUHALT_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_MCUHALT_MASK) >> NDP120_SPI_CTL_MCUHALT_SHIFT)
#define NDP120_SPI_CTL_MCUHALT_DEFAULT 0x00000000U
#define NDP120_SPI_CTL_EXTSEL_SHIFT 4
#define NDP120_SPI_CTL_EXTSEL_MASK 0x10U
#define NDP120_SPI_CTL_EXTSEL(v) \
        ((v) << NDP120_SPI_CTL_EXTSEL_SHIFT)
#define NDP120_SPI_CTL_EXTSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_EXTSEL_SHIFT))
#define NDP120_SPI_CTL_EXTSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_EXTSEL_MASK) | ((v) << NDP120_SPI_CTL_EXTSEL_SHIFT))
#define NDP120_SPI_CTL_EXTSEL_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_EXTSEL_MASK) >> NDP120_SPI_CTL_EXTSEL_SHIFT)
#define NDP120_SPI_CTL_EXTSEL_DEFAULT 0x00000000U
#define NDP120_SPI_CTL_INTSEL_SHIFT 5
#define NDP120_SPI_CTL_INTSEL_MASK 0x20U
#define NDP120_SPI_CTL_INTSEL(v) \
        ((v) << NDP120_SPI_CTL_INTSEL_SHIFT)
#define NDP120_SPI_CTL_INTSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_INTSEL_SHIFT))
#define NDP120_SPI_CTL_INTSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_INTSEL_MASK) | ((v) << NDP120_SPI_CTL_INTSEL_SHIFT))
#define NDP120_SPI_CTL_INTSEL_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_INTSEL_MASK) >> NDP120_SPI_CTL_INTSEL_SHIFT)
#define NDP120_SPI_CTL_INTSEL_DEFAULT 0x00000000U
#define NDP120_SPI_CTL_FLASHCTL_SHIFT 6
#define NDP120_SPI_CTL_FLASHCTL_MASK 0x40U
#define NDP120_SPI_CTL_FLASHCTL(v) \
        ((v) << NDP120_SPI_CTL_FLASHCTL_SHIFT)
#define NDP120_SPI_CTL_FLASHCTL_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_FLASHCTL_SHIFT))
#define NDP120_SPI_CTL_FLASHCTL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_FLASHCTL_MASK) | ((v) << NDP120_SPI_CTL_FLASHCTL_SHIFT))
#define NDP120_SPI_CTL_FLASHCTL_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_FLASHCTL_MASK) >> NDP120_SPI_CTL_FLASHCTL_SHIFT)
#define NDP120_SPI_CTL_FLASHCTL_DEFAULT 0x00000001U
#define NDP120_SPI_CTL_FLASHCTL_DISABLE 0x0U
#define NDP120_SPI_CTL_FLASHCTL_ENABLE 0x1U
#define NDP120_SPI_CTL_FLASHCTL_MAX 0x1U
#define NDP120_SPI_CTL_FLASHCTL_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_SPI_CTL_LOCKED_SHIFT 7
#define NDP120_SPI_CTL_LOCKED_MASK 0x80U
#define NDP120_SPI_CTL_LOCKED(v) \
        ((v) << NDP120_SPI_CTL_LOCKED_SHIFT)
#define NDP120_SPI_CTL_LOCKED_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CTL_LOCKED_SHIFT))
#define NDP120_SPI_CTL_LOCKED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CTL_LOCKED_MASK) | ((v) << NDP120_SPI_CTL_LOCKED_SHIFT))
#define NDP120_SPI_CTL_LOCKED_EXTRACT(x) \
        (((x) & NDP120_SPI_CTL_LOCKED_MASK) >> NDP120_SPI_CTL_LOCKED_SHIFT)
#define NDP120_SPI_CTL_DEFAULT 0x00000047U 
/* register ndp120_spi.cfg */
#define NDP120_SPI_CFG 0x12U
#define NDP120_SPI_CFG_THREE_WIRE_SHIFT 0
#define NDP120_SPI_CFG_THREE_WIRE_MASK 0x01U
#define NDP120_SPI_CFG_THREE_WIRE(v) \
        ((v) << NDP120_SPI_CFG_THREE_WIRE_SHIFT)
#define NDP120_SPI_CFG_THREE_WIRE_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CFG_THREE_WIRE_SHIFT))
#define NDP120_SPI_CFG_THREE_WIRE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CFG_THREE_WIRE_MASK) | ((v) << NDP120_SPI_CFG_THREE_WIRE_SHIFT))
#define NDP120_SPI_CFG_THREE_WIRE_EXTRACT(x) \
        (((x) & NDP120_SPI_CFG_THREE_WIRE_MASK) >> NDP120_SPI_CFG_THREE_WIRE_SHIFT)
#define NDP120_SPI_CFG_THREE_WIRE_DEFAULT 0x00000000U
#define NDP120_SPI_CFG_OPEN_DRAIN_SHIFT 1
#define NDP120_SPI_CFG_OPEN_DRAIN_MASK 0x02U
#define NDP120_SPI_CFG_OPEN_DRAIN(v) \
        ((v) << NDP120_SPI_CFG_OPEN_DRAIN_SHIFT)
#define NDP120_SPI_CFG_OPEN_DRAIN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CFG_OPEN_DRAIN_SHIFT))
#define NDP120_SPI_CFG_OPEN_DRAIN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CFG_OPEN_DRAIN_MASK) | ((v) << NDP120_SPI_CFG_OPEN_DRAIN_SHIFT))
#define NDP120_SPI_CFG_OPEN_DRAIN_EXTRACT(x) \
        (((x) & NDP120_SPI_CFG_OPEN_DRAIN_MASK) >> NDP120_SPI_CFG_OPEN_DRAIN_SHIFT)
#define NDP120_SPI_CFG_OPEN_DRAIN_DEFAULT 0x00000000U
#define NDP120_SPI_CFG_DRIVE_SHIFT 2
#define NDP120_SPI_CFG_DRIVE_MASK 0x0cU
#define NDP120_SPI_CFG_DRIVE(v) \
        ((v) << NDP120_SPI_CFG_DRIVE_SHIFT)
#define NDP120_SPI_CFG_DRIVE_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CFG_DRIVE_SHIFT))
#define NDP120_SPI_CFG_DRIVE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CFG_DRIVE_MASK) | ((v) << NDP120_SPI_CFG_DRIVE_SHIFT))
#define NDP120_SPI_CFG_DRIVE_EXTRACT(x) \
        (((x) & NDP120_SPI_CFG_DRIVE_MASK) >> NDP120_SPI_CFG_DRIVE_SHIFT)
#define NDP120_SPI_CFG_DRIVE_DEFAULT 0x00000000U
#define NDP120_SPI_CFG_DRIVE_DRIVE2MA 0x0U
#define NDP120_SPI_CFG_DRIVE_DRIVE4MA 0x1U
#define NDP120_SPI_CFG_DRIVE_DRIVE6MA 0x2U
#define NDP120_SPI_CFG_DRIVE_DRIVE8MA 0x3U
#define NDP120_SPI_CFG_DRIVE_MAX 0x3U
#define NDP120_SPI_CFG_DRIVE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_SPI_CFG_INTEN_SHIFT 4
#define NDP120_SPI_CFG_INTEN_MASK 0x10U
#define NDP120_SPI_CFG_INTEN(v) \
        ((v) << NDP120_SPI_CFG_INTEN_SHIFT)
#define NDP120_SPI_CFG_INTEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CFG_INTEN_SHIFT))
#define NDP120_SPI_CFG_INTEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CFG_INTEN_MASK) | ((v) << NDP120_SPI_CFG_INTEN_SHIFT))
#define NDP120_SPI_CFG_INTEN_EXTRACT(x) \
        (((x) & NDP120_SPI_CFG_INTEN_MASK) >> NDP120_SPI_CFG_INTEN_SHIFT)
#define NDP120_SPI_CFG_INTEN_DEFAULT 0x00000000U
#define NDP120_SPI_CFG_INTNEG_SHIFT 5
#define NDP120_SPI_CFG_INTNEG_MASK 0x20U
#define NDP120_SPI_CFG_INTNEG(v) \
        ((v) << NDP120_SPI_CFG_INTNEG_SHIFT)
#define NDP120_SPI_CFG_INTNEG_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CFG_INTNEG_SHIFT))
#define NDP120_SPI_CFG_INTNEG_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CFG_INTNEG_MASK) | ((v) << NDP120_SPI_CFG_INTNEG_SHIFT))
#define NDP120_SPI_CFG_INTNEG_EXTRACT(x) \
        (((x) & NDP120_SPI_CFG_INTNEG_MASK) >> NDP120_SPI_CFG_INTNEG_SHIFT)
#define NDP120_SPI_CFG_INTNEG_DEFAULT 0x00000000U
#define NDP120_SPI_CFG_QSPI_ENABLE_SHIFT 6
#define NDP120_SPI_CFG_QSPI_ENABLE_MASK 0x40U
#define NDP120_SPI_CFG_QSPI_ENABLE(v) \
        ((v) << NDP120_SPI_CFG_QSPI_ENABLE_SHIFT)
#define NDP120_SPI_CFG_QSPI_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CFG_QSPI_ENABLE_SHIFT))
#define NDP120_SPI_CFG_QSPI_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CFG_QSPI_ENABLE_MASK) | ((v) << NDP120_SPI_CFG_QSPI_ENABLE_SHIFT))
#define NDP120_SPI_CFG_QSPI_ENABLE_EXTRACT(x) \
        (((x) & NDP120_SPI_CFG_QSPI_ENABLE_MASK) >> NDP120_SPI_CFG_QSPI_ENABLE_SHIFT)
#define NDP120_SPI_CFG_QSPI_ENABLE_DEFAULT 0x00000000U
#define NDP120_SPI_CFG_BURST4_SHIFT 7
#define NDP120_SPI_CFG_BURST4_MASK 0x80U
#define NDP120_SPI_CFG_BURST4(v) \
        ((v) << NDP120_SPI_CFG_BURST4_SHIFT)
#define NDP120_SPI_CFG_BURST4_INSERT(x, v) \
        ((x) | ((v) << NDP120_SPI_CFG_BURST4_SHIFT))
#define NDP120_SPI_CFG_BURST4_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SPI_CFG_BURST4_MASK) | ((v) << NDP120_SPI_CFG_BURST4_SHIFT))
#define NDP120_SPI_CFG_BURST4_EXTRACT(x) \
        (((x) & NDP120_SPI_CFG_BURST4_MASK) >> NDP120_SPI_CFG_BURST4_SHIFT)
#define NDP120_SPI_CFG_BURST4_DEFAULT 0x00000000U
#define NDP120_SPI_CFG_DEFAULT 0x00000000U 
/* register ndp120_spi.sample */
#define NDP120_SPI_SAMPLE 0x20U
/* register ndp120_spi.mbin */
#define NDP120_SPI_MBIN 0x30U
/* register ndp120_spi.mbin_resp */
#define NDP120_SPI_MBIN_RESP 0x31U
/* register ndp120_spi.mbout */
#define NDP120_SPI_MBOUT 0x32U
/* register ndp120_spi.mbout_resp */
#define NDP120_SPI_MBOUT_RESP 0x33U
/* register array ndp120_spi.maddr[4] */
#define NDP120_SPI_MADDR(i) (0x40U + ((i) << 0))
#define NDP120_SPI_MADDR_COUNT 4
/* register array ndp120_spi.mdata[4] */
#define NDP120_SPI_MDATA(i) (0x44U + ((i) << 0))
#define NDP120_SPI_MDATA_COUNT 4
/* register array ndp120_spi.mdummy[12] */
#define NDP120_SPI_MDUMMY(i) (0x48U + ((i) << 0))
#define NDP120_SPI_MDUMMY_COUNT 12
#define NDP120_SPI_MATCH_WINNER_MASK 0x3fU
#define NDP120_SPI_MATCH_WINNER_SHIFT 0
#define NDP120_SPI_MATCH_WINNER_EXTRACT(x) \
        (((x) & NDP120_SPI_MATCH_WINNER_MASK) >> NDP120_SPI_MATCH_WINNER_SHIFT)

#endif
